Verilog

Text::EP3::Verilog Perl module contains a verilog extension for the EP3 preprocessor. SYNOPSIS use Text::EP3; use Text::EP3::Verilog; This module is an EP3 extension for the Verilog Hardware Description Language. The signal directive @signal key definition Take a list of signals and...

Verilog::Netlist::Net is a Net for a Verilog Module. SYNOPSIS use Verilog::Netlist; ... my $net = $module->find_net (signalname); print $net->name; Verilog::Netlist creates a net for every sc_signal declaration in the current module..

Verilog::CodeGen module is a Verilog code generator. SYNOPSIS use Verilog::CodeGen; mkdir DeviceLibs/Objects/YourDesign, 0755; chdir DeviceLibs/Objects/YourDesign; # if the directory YourDesign exists, the second argument can be omitted # create YourModule.pl in YourDesign...


Platforms: *nix

vrq is verilog parser that supports plugin tools to process verilog. Current plugins include tools to perform x-propagation and to auto build hiearchy.


Platforms: Mac

Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.


Platforms: Windows, Mac, Linux

Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.


Platforms: Windows, Mac, BSD, Linux

Verilog-A Implementation of the Mextram Bipolar Transistor Model


Platforms: Windows, Mac, Linux

PVSim is a Verilog Simulator for Mac OS X that uses AlphaX editor's Verilog mode and features a fast compile-simulate-display cycle.


Platforms: Mac, BSD, Linux

VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.


Platforms: *nix, Perl, BSD Solaris

GTKWave is VCD/EVCD/LXT/Synopsis .out format electronic waveform viewer built using the GTK+ toolkit. The project was originally developed by Tony Bybell but development has now passed to the APT group and we hope to extend and improve GTKWave to support new formats and features. Installation...


Platforms: Mac

VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.


Platforms: *nix

Hardware::Simulator is a Perl extension for Perl Hardware Descriptor Language. SYNOPSIS use Hardware::Simulator; # NewSignal( perl_variable [, initial_value]); # create a signal called $in_clk, give it an initial value of 1 NewSignal(my $in_clk,1); # Repeater ( time_units , code_ref) #...


Platforms: *nix

Qfsm is a graphical editor for finite state machines written in C++ using Qt the graphical Toolkit from Trolltech. Finite state machines are a model to describe complex objects or systems in terms of the states they may be in. In practice they can used to design integrated circuits or to create...


Platforms: *nix

SVEditor is an Eclipse-based editor for SystemVerilog and Verilog files. It features syntax coloring, content assist, source indent and auto-indent, and structure display.


Platforms: Mac

XOR Tree Generator is a small, easy to use application specially designed to offer users a tool to help them create Verilog synthesizable XOR trees for high performance designs. This utility supports the creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers. for WindowsAll


Platforms: Windows

Gorgeous Karnaugh software: 1) Removes slow, tedious and error prone pen and paper from your life; 2) Gives you a pretty good logic simplification tool; 3) Supports definition of logic function using truth table, from analytic form or by direct editing karnaugh maps; 4) Supports "Dont Care"...


Platforms: Windows

Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.


Platforms: Windows, Mac, BSD, Linux

Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.


Platforms: Windows, Mac, Linux

vIDE is a cross-platform tool for writing and simulating Verilog models. It provides user friendly project management and file editing, integrated simulation engine, waveform viewer, pre-compiled modules, and many other cool features.


Platforms: Windows, Mac, Linux

A brand-new powerful major mode for editing verilog sources in Emacs.


Platforms: Windows, Mac, Linux