Verilog

This demo consists of a m-file script (fixed_point_atan2_using_cordic.m) and a m-file function (atan2_fixpt.m). The script contains a step-by-step explanation of how a four quadrant arctan can be calculated using a CORDIC (COordinate Rotation DIgital Computer) algorithm. The first part shows the... Platforms: Matlab

For a full description of the models, refer to the September 2007 MATLAB Digest article.http://www.mathworks.com/company/newslette...sigmadelta.htmlWe present a series of Simulink models to design a high-level behavioral model of a Sigma-Delta ADC. The high-level behavioral model has an Analog... Platforms: Matlab

zamiaCAD is a modular and extensible platform for advanced hardware design, analysis, and research. Its core components are the language independent Instantiation Graph (IG) data structure, the language dependent frontends generating an IG, and applications working on the IG data structure. The... Platforms: Mac

Sister is high-level synthesizer for SoC design . It analyzes SystemC(based on C++ language) source code and creates Verilog HDL source code. Platforms: *nix

Scicos-HDL integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. Scicos-HDL shortens digital circuit design cycles by helping you create the hardware representation in an... Platforms: *nix

This utility has been developed for those who wants to convert an existing verilog design into VHDL. The generated VHDL may not work as is and may require some manual correction to ensure the VHDL data type matching. This has been developed in Java( 1.6.x ) in order to make it platform... Platforms: *nix

EP3 Perl module is the Extensible Perl PreProcessor. SYNOPSIS # Use options and files from command-line use Text::EP3; [use Text::EP3::{Extension}] # Language Specific Modules # create the PreProcessor object my $preprocessor = new Text::EP3 file; # do the preprocessing, using... Platforms: *nix

SystemC::SystemPerl is a SystemPerl Language Extension to SystemC. SystemPerl is a version of the SystemC language. It is designed to expand text so that needless repetition in the language is minimized. By using sp_preproc, SystemPerl files can be expanded into C++ files at compile time, or... Platforms: *nix

SystemC::Netlist::Net is a Perl module which provides Net for a SystemC Module. This is a superclass of Verilog::Netlist::Net, derived for a SystemC netlist pin. Parsing example: @example package Trialparser; @@ISA = qw(SystemC::Parser); sub module @{ my $self = shift; my $module =... Platforms: *nix

FIR HDL Writer is an EDA tool which generates FIR filters in clear text Verilog which may be synthesized to FPGA's or ASIC's. Design options include multiple channels, coefficient sets, interpolation, decimation, and resource utilization specifications. The designs are fully synchronous and... Platforms: Mac

Qucs is a circuit simulator with graphical user interface. The software aims to support all kinds of circuit simulation types, e.g. DC, AC, S-parameter, Harmonic Balance analysis, noise analysis, etc. Until now there is no or little user documentation available. The Qucs application has an... Platforms: Windows, Mac, Linux

Robei is the world smallest EDA tool for FPGA design and simulation. With this tool, you can design your hardware visually at anywhere, and view the simulation result through waveform. It is a tiny, fast software for hardware prototyping and verification. Imagine that when you are waiting for a... Platforms: Windows

CoreTML framework is an open-source template-based configuration system (template engine). It allows the developer to create parametrized templates by inserting special content to any text files. These templates can later be used to generate output files depending upon parameters chosen by the... Platforms: Windows

HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future. Platforms: Windows, Mac, Linux

This project deals with the translation of a Simulink models to SpecC specificationmodels. Matlab is one of the leading softwares in model based and algorithmic designing. SpecC (close to ANSI C) is a high level language which can be implemented on hardware usingSystem on Chip Environment(SCE).... Platforms: Matlab

Use xilinxbram.m and xilinxbraminit.m functions to generate VHDL or Verilog fraction of code to initialize Xilinx FPGA (Spartan, Virtex) 18k block RAM.Recent revision is also available here: http://radio.feld.cvut.cz/personal/matejka...oot:en:projects Platforms: Matlab

This utility is very useful for those designer(s) who does not know the order of their RTL files and/or does not know which file to compile in which library. It takes all the RTL files as input and then process those files internally and come up with a sorted/ordered list of files along with... Platforms: Mac

DParser is an simple but powerful tool for parsing. You can specify the form of the text to be parsed using a combination of regular expressions and grammar productions. Because of the parsing technique (technically a scannerless GLR parser based on the Tomita algorithm) there are no... Platforms: *nix

TkGate is a event driven digital circuit simulator with a tcl/tk-based graphical editor. TkGate supports a wide range of primitive circuit elements as well as user-defined modules for hierarchical design. The distribution comes with a number of tutorial and example circuits which can be loaded... Platforms: *nix

SRecord is a collection of powerful tools for manipulating EPROM load files. SRecord project understands a number of file formats including Motorola S-Record, Intel hex, Tektronix hex and binary, for both input and output. SRecord filters include cropping, filling, splitting, joining, and more.... Platforms: *nix