scicosHDL 6

Scicos-HDL integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. Scicos-HDL shortens digital circuit design cycles by helping you create the hardware representation in an modeling-friendly development environment. You can combine existing Scicos blocks with Scicos-HDL blocks and to link system-level design . It is a open source project under Scilab ???*?s license, the release vision can help to design and simulate some small-scale digital circuit system with its Hardware Description Language generation. We now will make it as a tool for teaching digital circuit design. Now it supports SystemC, VHDL&Verilog Languages.<br /><br />Features:<br /><br /> Links The Scilab/Scicos with the Digital circuit design(EDA).<br /><br /> Integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation.<br /><br /> Enables complex signal processing combined with powerful mathematical tools.<br /><br /> Inside libraries: Sequential logic library, Combinational logic library, Ipcore library, simulation library.<br /><br /> Support mixed-simulation with the Scicos blocks.<br /><br /> Automatically generates Description Language(SystemC ,VHDL and Verilog ).<br /><br /> Automatic propagation of signal names to generated HDL.<br /><br /> You can specify most values in the block parameter dialog boxes using Scicos workspace.<br /><br /> Mix-simulation with original Scicos blocks and Scicos-HDL blocks.<br /><br /> Open interface for users to add blocks.<br /><br /> Under GPL LICENCE.<br />

Requirements:	No special requirements
Platforms:	*nix, Linux
Keyword:	Blocks,  Combine,  Existing,  Languages,  License,  Project,  Release,  Scicos,  Scilab,  Simulate,  Smallscale,  Source,  Supports,  System,  Systemc,  Systemlevel,  Teaching,  Vhdl Verilog,  Vision
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