Verilogcodegen

Verilog::CodeGen module is a Verilog code generator. SYNOPSIS use Verilog::CodeGen; mkdir DeviceLibs/Objects/YourDesign, 0755; chdir DeviceLibs/Objects/YourDesign; # if the directory YourDesign exists, the second argument can be omitted # create YourModule.pl in YourDesign...


Platforms: *nix