Verilog Hdl

MB Free Cholesterol Risk Calculator is a simple health software with an easy to use interface. The program is designed to calculate the risk of a person suffering from a heart attack in the next ten years depending on cholesterol levels and their effects. Blood Cholesterol level is one of major... Platforms: Windows

Qucs is a circuit simulator with graphical user interface. The software aims to support all kinds of circuit simulation types, e.g. DC, AC, S-parameter, Harmonic Balance analysis, noise analysis, etc. Until now there is no or little user documentation available. The Qucs application has an... Platforms: Windows, Mac, Linux

Verilog::Netlist::Net is a Net for a Verilog Module. SYNOPSIS use Verilog::Netlist; ... my $net = $module->find_net (signalname); print $net->name; Verilog::Netlist creates a net for every sc_signal declaration in the current module.. Platforms: *nix

Qfsm is a graphical editor for finite state machines written in C++ using Qt the graphical Toolkit from Trolltech. Finite state machines are a model to describe complex objects or systems in terms of the states they may be in. In practice they can used to design integrated circuits or to create... Platforms: *nix

Verilog::CodeGen module is a Verilog code generator. SYNOPSIS use Verilog::CodeGen; mkdir DeviceLibs/Objects/YourDesign, 0755; chdir DeviceLibs/Objects/YourDesign; # if the directory YourDesign exists, the second argument can be omitted # create YourModule.pl in YourDesign... Platforms: *nix

Text::EP3::Verilog Perl module contains a verilog extension for the EP3 preprocessor. SYNOPSIS use Text::EP3; use Text::EP3::Verilog; This module is an EP3 extension for the Verilog Hardware Description Language. The signal directive @signal key definition Take a list of signals and... Platforms: *nix

Gorgeous Karnaugh software: 1) Removes slow, tedious and error prone pen and paper from your life; 2) Gives you a pretty good logic simplification tool; 3) Supports definition of logic function using truth table, from analytic form or by direct editing karnaugh maps; 4) Supports "Dont Care"... Platforms: Windows

asfpga is an assembler written for use in FPGA design. It can be easily modified for your instruction set. The ultimate goal of this software is to allow a FPGA designer to easily write assembly code for a custom instruction set. The current version allows to create a listing file, a memory... Platforms: *nix

SystemC::SystemPerl is a SystemPerl Language Extension to SystemC. SystemPerl is a version of the SystemC language. It is designed to expand text so that needless repetition in the language is minimized. By using sp_preproc, SystemPerl files can be expanded into C++ files at compile time, or... Platforms: *nix

Knoppix Elphel is a Live CD based in Knoppix 4.0.2. This release includes new AJAX GUI (camvc) with DVR capability in addition to the earlier developed software. Archive (LiveCD-1.5.0.build.tar) include all files, needed for build live CD/DVD manually, except original CD/DVD images. Please... Platforms: *nix

Hardware::Simulator is a Perl extension for Perl Hardware Descriptor Language. SYNOPSIS use Hardware::Simulator; # NewSignal( perl_variable [, initial_value]); # create a signal called $in_clk, give it an initial value of 1 NewSignal(my $in_clk,1); # Repeater ( time_units , code_ref) #... Platforms: *nix

EP3 Perl module is the Extensible Perl PreProcessor. SYNOPSIS # Use options and files from command-line use Text::EP3; [use Text::EP3::{Extension}] # Language Specific Modules # create the PreProcessor object my $preprocessor = new Text::EP3 file; # do the preprocessing, using... Platforms: *nix

SystemC::Netlist::Net is a Perl module which provides Net for a SystemC Module. This is a superclass of Verilog::Netlist::Net, derived for a SystemC netlist pin. Parsing example: @example package Trialparser; @@ISA = qw(SystemC::Parser); sub module @{ my $self = shift; my $module =... Platforms: *nix

vIDE is a cross-platform tool for writing and simulating Verilog models. It provides user friendly project management and file editing, integrated simulation engine, waveform viewer, pre-compiled modules, and many other cool features. Platforms: Windows, Mac, Linux

VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches. Platforms: *nix, Perl, BSD Solaris

Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL. Platforms: Windows, Mac, Linux

DParser is an simple but powerful tool for parsing. You can specify the form of the text to be parsed using a combination of regular expressions and grammar productions. Because of the parsing technique (technically a scannerless GLR parser based on the Tomita algorithm) there are no... Platforms: *nix

SVEditor is an Eclipse-based editor for SystemVerilog and Verilog files. It features syntax coloring, content assist, source indent and auto-indent, and structure display. Platforms: Mac

Robei is the world smallest EDA tool for FPGA design and simulation. With this tool, you can design your hardware visually at anywhere, and view the simulation result through waveform. It is a tiny, fast software for hardware prototyping and verification. Imagine that when you are waiting for a... Platforms: Windows

Software and HDL code for Elphel reconfigurable network cameras Platforms: Windows, Mac, Linux