Synthesizable

XOR Tree Generator is a small, easy to use application specially designed to offer users a tool to help them create Verilog synthesizable XOR trees for high performance designs. This utility supports the creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers. for WindowsAll


Platforms: Windows

BlowfishVHDL - free fully synthesizable Blowfish encryption algorithm hardware implementation.


Platforms: Windows, Mac, Linux

Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.


Platforms: Windows, Mac, BSD, Linux

This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL).The step-wise...


Platforms: Matlab