Download - FIR HDL Writer 0.9

FIR HDL Writer 0.9

FIR HDL Writer is an EDA tool which generates FIR filters in clear text Verilog which may be synthesized to FPGA's or ASIC's. Design options include multiple channels, coefficient sets, interpolation, decimation, and resource utilization specifications. The designs are fully synchronous and registered to provide maximum clock frequencies. Clock rates in excess of 300 MHz have been observed with Stratix II and Virtex IV devices (using Quartus...

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